1. Field of the Invention
The present invention relates to a method of simulating expansion and contraction amount of a wafer, and particularly to a simulation method for the expansion and contraction amount of a wafer in a thin film growth process.
2. Description of the Related Art
Recently, large-scale integrated circuits (hereinafter referred to as "LSI") has been designed in a more minute structure and semiconductor wafers have been designed to have a large diameter, and such a tendency has made more critical the expansion and contraction of the wafers induced in a thin film growth process for manufacturing an LSI chip.
Some countermeasures have been taken to solve the above problem, and it has been indispensable to establish a simulation method for the expansion and contraction of wafers in order to enhance the efficiency of the developments of the devices.
In an example of a method of simulating the expansion and contraction of wafers by using a conventional technique, a displacement amount is calculated on the basis of a thermal stress simulation using a finite element method when a thermal load and a restraint are given as disclosed by Hamajima, et al. in Extended Abstracts (The 40th Spring Meeting, 1993); The Japan Society of Applied Physics and Related Societies, p. 733. FIG. 1 is a diagram showing a case where a simulation of the expansion and contraction of a wafer in a thin film growth process is performed by using the conventional technique.
In a first stage, a thermal stress analysis when the temperature of a silicon wafer 1 is increased from the room temperature to the film forming temperature as shown at the upper side (a) of FIG. 1 is performed. Reference numerals 2a and 2a' denote the wafer at the room temperature and the film forming temperature, respectively. The residual stress values .sigma.s1r, .sigma.s1z, .sigma.s1.theta., .tau.s1rz and the displacement values us1r, us1z are reserved.
In a second stage, as shown at the lower side (b) of FIG. 1, a thermal stress analysis when a thin film 2 made of Si.sub.3 N.sub.4 is formed on the silicon wafer 1 having the residual stress .sigma.s1 and the displacement us1, which have been reserved in the first stage, and the temperature is decreased from the film forming temperature to the room temperature. Reference numerals 2b and 2b' denote the wafer and thin film at the film forming temperature and the room temperature, respectively. The residual stress values .sigma.s2r, .sigma.s2z, .sigma.s2.theta., .tau.s2rz and the displacement values us2r and us2z of the wafer 1 thus obtained and the residual stress values .sigma.f2r, .sigma.f2z, .sigma.f2.theta., .tau.f2rz and the displacement values uf2r and uf2z of the thin film 2 are determined. In the conventional technique, the displacement values us2r and us2z of the wafer which are obtained in the second stage are set as the expansion-and-contraction amount of the wafer in the thin film forming process.
The conventional technique has the following problems.
A first problem resides in that the residual stress values must be kept in each step, so that the data storage amount is large and the large storage capacity (memory capacity, disc capacity) is necessary.
A second problem resides in that a time period for calculation processing due to data read-out is increased in each step.
A third problem resides in that a result obtained by calculating the displacement in the film forming process of Si.sub.3 N.sub.4 by using the conventional method is greatly different from the actual measurement result. This is because the conventional technique takes no consideration of the intrinsic stress in the film forming process.